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MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
September 1983 Revised February 1999
MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a gated CLOCK input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function. Holding either of the CLOCK inputs high inhibits clocking, and holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the SHIFT/LOAD input is HIGH. When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 20 ns (clock to Q) s Wide operating supply voltage range: 2-6V s Low input current: 1 A maximum s Low quiescent supply current: 80 A maximum (74HC Series) s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number MM74HC165M MM74HC165SJ MM74HC165MTC MM74HC165 Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Function Table
Inputs Internal Output QH h QH0 QGN QGN QH0 A. . .H QA X L X X X H L X a. . .h X X X X a H L QB b QAN QAN Shift/ Clock Clock Serial Parallel Outputs Load Inhibit L H H H H X L L L H
QA0 QB0
QA0 QB0
H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions) = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAN, QGN = The level of QA or QG before the most recent transition of the clock; indicates a one-bit shift.
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(c) 1999 Fairchild Semiconductor Corporation
DS005316.prf
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MM74HC165
Logic Diagrams
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MM74HC165
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 -40 VCC +85 V C 2 Max 6 Units V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 Units V V V V V V V V V V V V V V V V A A
Conditions
VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA 4.5V 6.0V 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA 4.5V 6.0V 6.0V 6.0V
VOL
Maximum LOW Level Output Voltage
VIN = VIH or VIL |IOUT| 20 A
IIN ICC
Maximum Input Current Maximum Quiescent Supply Current
VIN = VCC or GND VCC = 2-6V VIN = VCC or GND IOUT = 0 A VCC = 2-6V
Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC165
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL, tPLH tPHL, tPLH tS tS tS tH Parameter Maximum Operating Frequency Maximum Propagation Delay H to QH or Q H Maximum Propagation Delay Serial Shift/Parallel Load to QH Maximum Propagation Delay Clock to Output Minimum Setup Time Serial Input to Clock, Parallel or Data to Shift/Load Minimum Setup Time Shift/Load to Clock Minimum Setup Time Clock Inhibit to Clock Minimum Hold Time Serial Input to Clock or Parallel Data to Shift/Load tW Minimum Pulse Width Clock 16 ns 11 10 20 20 0 ns ns ns 10 20 ns 15 25 ns Conditions Typ 50 15 13 Guaranteed Limit 30 25 25 Units MHz ns ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay H to QH or Q H tPHL, tPLH Maximum Propagation Delay Serial Shift/ Parallel Load to QH tPHL, tPLH Maximum Propagation Delay Clock to Output tS Minimum Setup Time Serial Input to Clock, or Parallel Data to Shift/Load tS Minimum Setup Time Shift/Load to Clock tS Minimum Setup Time Clock Inhibit to Clock tH Minimum Hold Time Serial Input to Clock or Parallel Data to Shift/Load tW Minimum Pulse Width, Clock tTHL, tTLH Maximum Output Rise and Fall Time tr, tf Maximum Input Rise and Fall Time Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 30 9 8 30 9 8 TA = 25C Typ 10 45 50 70 21 18 70 21 18 70 21 18 35 11 9 38 12 9 35 11 9 5 27 32 150 30 26 175 35 30 150 30 26 100 20 17 100 20 17 100 20 17 0 0 0 80 16 14 75 15 13 1000 500 400 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 4 21 25 189 38 33 220 44 37 189 38 33 125 25 21 125 25 21 125 25 21 0 0 0 100 20 18 95 19 16 1000 500 400 4 18 21 225 45 39 260 52 44 225 45 39 150 30 25 150 30 25 150 30 25 0 0 0 120 24 20 110 22 19 1000 500 400 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
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MM74HC165
AC Electrical Characteristics
Symbol CPD CIN Parameter Power Dissipation Capacitance (Note 5) Maximum Input Capacitance
(Continued)
TA = 25C Typ 100 5 10 10 10 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits pF pF
Conditions (per package)
VCC
Units
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
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MM74HC165
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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MM74HC165
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300" Wide Package N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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